Initializing gui preferences from file  /var/home/vv8dn/.synopsys_dv_prefs.tcl
dc_shell> source ../scripts/setup2.tcl
dc_shell> source ../scripts/design.tcl
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/saed90nm_typ_ht.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/saed90nm_typ_htm.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/saed90nm_typ_htl.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/saed90nm_min_htl.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/clock_gating/saed90nm_typ_ht_cg.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/clock_gating/saed90nm_typ_htm_cg.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/clock_gating/saed90nm_typ_htl_cg.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/clock_gating/saed90nm_min_htl_cg.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/retention/saed90nm_typ_ht_rd.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/retention/saed90nm_typ_htm_rd.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/retention/saed90nm_typ_htl_rd.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/retention/saed90nm_min_htl_rd.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters/saed90nm_min_htln_lsh.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters/saed90nm_typ_hthh_lsh.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters/saed90nm_typ_hthn_lsh.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters/saed90nm_typ_htln_lsh.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters/saed90nm_max_htln_lsh.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters/saed90nm_typ_hthm_lsh.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters/saed90nm_typ_htmm_lsh.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/isoao/saed90nm_min_htln_iso.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/isoao/saed90nm_typ_hthh_iso.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/isoao/saed90nm_typ_htln_iso.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/isoao/saed90nm_max_htln_iso.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/isoao/saed90nm_typ_htmm_iso.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters_ss/saed90nm_min_htln_lshss.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters_ss/saed90nm_typ_hthh_lshss.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters_ss/saed90nm_typ_hthn_lshss.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters_ss/saed90nm_typ_htln_lshss.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters_ss/saed90nm_max_htln_lshss.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters_ss/saed90nm_typ_hthm_lshss.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters_ss/saed90nm_typ_htmm_lshss.db'
Loading db file '/app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/gtech.db'
Loading db file '/app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/standard.sldb'
  Loading link library 'saed90nm_typ_ht'
  Loading link library 'saed90nm_typ_htm'
  Loading link library 'saed90nm_typ_htl'
  Loading link library 'saed90nm_min_htl'
  Loading link library 'saed90nm_typ_ht_cg'
  Loading link library 'saed90nm_typ_htm_cg'
  Loading link library 'saed90nm_typ_htl_cg'
  Loading link library 'saed90nm_min_htl_cg'
  Loading link library 'saed90nm_typ_ht_rd'
  Loading link library 'saed90nm_typ_htm_rd'
  Loading link library 'saed90nm_typ_htl_rd'
  Loading link library 'saed90nm_min_htl_rd'
  Loading link library 'saed90nm_min_htln_lsh'
  Loading link library 'saed90nm_typ_hthh_lsh'
  Loading link library 'saed90nm_typ_hthn_lsh'
  Loading link library 'saed90nm_typ_htln_lsh'
  Loading link library 'saed90nm_max_htln_lsh'
  Loading link library 'saed90nm_typ_hthm_lsh'
  Loading link library 'saed90nm_typ_htmm_lsh'
  Loading link library 'saed90nm_min_htln_iso'
  Loading link library 'saed90nm_typ_hthh_iso'
  Loading link library 'saed90nm_typ_htln_iso'
  Loading link library 'saed90nm_max_htln_iso'
  Loading link library 'saed90nm_typ_htmm_iso'
  Loading link library 'saed90nm_min_htln_lshss'
  Loading link library 'saed90nm_typ_hthh_lshss'
  Loading link library 'saed90nm_typ_hthn_lshss'
  Loading link library 'saed90nm_typ_htln_lshss'
  Loading link library 'saed90nm_max_htln_lshss'
  Loading link library 'saed90nm_typ_hthm_lshss'
  Loading link library 'saed90nm_typ_htmm_lshss'
  Loading link library 'gtech'
Loading verilog file '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu.v'
Detecting input file type automatically (-rtl or -netlist).
Running DC verilog reader
Opening include file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_defines.v
Opening include file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_pre_norm_mul.v
Reading with Presto HDL Compiler (equivalent to -rtl option).
Running PRESTO HDLC
Compiling source file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu.v
Searching for /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/or1200_defines.v
Searching for /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_defines.v
Opening include file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_defines.v
Searching for /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/or1200_fpu_pre_norm_mul.v
Searching for /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_pre_norm_mul.v
Opening include file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_pre_norm_mul.v
Searching for /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/or1200_fpu_pre_norm_div.v
Searching for /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_pre_norm_div.v
Opening include file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_pre_norm_div.v
Searching for /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/or1200_fpu_pre_norm_addsub.v
Searching for /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_pre_norm_addsub.v
Opening include file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_pre_norm_addsub.v
Searching for /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/or1200_fpu_post_norm_mul.v
Searching for /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_mul.v
Opening include file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_mul.v
Searching for /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/or1200_fpu_post_norm_intfloat_conv.v
Searching for /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_intfloat_conv.v
Opening include file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_intfloat_conv.v
Searching for /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/or1200_fpu_post_norm_div.v
Searching for /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_div.v
Opening include file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_div.v
Searching for /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/or1200_fpu_post_norm_addsub.v
Searching for /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_addsub.v
Opening include file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_addsub.v
Searching for /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/or1200_fpu_mul.v
Searching for /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_mul.v
Opening include file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_mul.v
Searching for /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/or1200_fpu_intfloat_conv.v
Searching for /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv.v
Opening include file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv.v
Searching for /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/or1200_fpu_intfloat_conv_except.v
Searching for /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv_except.v
Opening include file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv_except.v
Searching for /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/or1200_fpu_fcmp.v
Searching for /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_fcmp.v
Opening include file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_fcmp.v
Searching for /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/or1200_fpu_div.v
Searching for /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_div.v
Opening include file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_div.v
Searching for /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/or1200_fpu_arith.v
Searching for /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_arith.v
Opening include file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_arith.v
Searching for /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/or1200_fpu_addsub.v
Searching for /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_addsub.v
Opening include file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_addsub.v

Inferred memory devices in process
        in routine or1200_fpu_pre_norm_mul line 90 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_pre_norm_mul.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    exp_10_o_reg     | Flip-flop |  10   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_pre_norm_div line 99 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_pre_norm_div.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    exp_10_o_reg     | Flip-flop |  10   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_pre_norm_div line 180 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_pre_norm_div.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    s_expa_in_reg    | Flip-flop |  10   |  Y  | N  | N  | N  | N  | N  | N  |
|    s_expb_in_reg    | Flip-flop |  10   |  Y  | N  | N  | N  | N  | N  | N  |
|   s_exp_10_o_reg    | Flip-flop |  10   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Statistics for case statements in always block at line 138 in file
        '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_pre_norm_addsub.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           140            |    auto/auto     |
===============================================

Inferred memory devices in process
        in routine or1200_fpu_pre_norm_addsub line 103 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_pre_norm_addsub.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      exp_o_reg      | Flip-flop |   8   |  Y  | N  | N  | N  | N  | N  | N  |
|   fracta_28_o_reg   | Flip-flop |  28   |  Y  | N  | N  | N  | N  | N  | N  |
|   fractb_28_o_reg   | Flip-flop |  28   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_pre_norm_addsub line 126 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_pre_norm_addsub.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     s_exp_o_reg     | Flip-flop |   8   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_pre_norm_addsub line 138 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_pre_norm_addsub.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|   s_exp_diff_reg    | Flip-flop |   8   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Statistics for case statements in always block at line 140 in file
        '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_mul.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           142            |    user/user     |
===============================================

Statistics for case statements in always block at line 195 in file
        '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_mul.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           196            |    user/user     |
===============================================

Inferred memory devices in process
        in routine or1200_fpu_post_norm_mul line 114 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_mul.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    s_rmode_i_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    s_sign_i_reg     | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|     s_opa_i_reg     | Flip-flop |  31   |  Y  | N  | N  | N  | N  | N  | N  |
|     s_opb_i_reg     | Flip-flop |  31   |  Y  | N  | N  | N  | N  | N  | N  |
|     s_expa_reg      | Flip-flop |   8   |  Y  | N  | N  | N  | N  | N  | N  |
|     s_expb_reg      | Flip-flop |   8   |  Y  | N  | N  | N  | N  | N  | N  |
|   s_exp_10_i_reg    | Flip-flop |  10   |  Y  | N  | N  | N  | N  | N  | N  |
|  s_fract_48_i_reg   | Flip-flop |  48   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_post_norm_mul line 127 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_mul.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    output_o_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      ine_o_reg      | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_post_norm_mul line 140 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_mul.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     s_zeros_reg     | Flip-flop |   6   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_post_norm_mul line 195 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_mul.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    s_r_zeros_reg    | Flip-flop |   6   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_post_norm_mul line 269 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_mul.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     s_shr2_reg      | Flip-flop |   6   |  Y  | N  | N  | N  | N  | N  | N  |
|     s_shl2_reg      | Flip-flop |   6   |  Y  | N  | N  | N  | N  | N  | N  |
|     s_expo1_reg     | Flip-flop |   9   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_post_norm_mul line 293 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_mul.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    s_frac2a_reg     | Flip-flop |  48   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_post_norm_mul line 325 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_mul.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|   s_frac_rnd_reg    | Flip-flop |  25   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Statistics for case statements in always block at line 388 in file
        '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_intfloat_conv.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           389            |    user/user     |
===============================================

Statistics for case statements in always block at line 395 in file
        '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_intfloat_conv.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           396            |    user/user     |
===============================================

Inferred memory devices in process
        in routine or1200_fpu_post_norm_intfloat_conv line 139 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_intfloat_conv.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     fi_ldz_reg      | Flip-flop |   6   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_post_norm_intfloat_conv line 210 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_intfloat_conv.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|   fract_in_00_reg   | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_post_norm_intfloat_conv line 282 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_intfloat_conv.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|   fract_trunc_reg   | Flip-flop |  25   |  Y  | N  | N  | N  | N  | N  | N  |
|    fract_out_reg    | Flip-flop |  23   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_post_norm_intfloat_conv line 319 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_intfloat_conv.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     exp_out_reg     | Flip-flop |   8   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_post_norm_div line 113 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_div.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    s_rmode_i_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    s_sign_i_reg     | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|     s_opa_i_reg     | Flip-flop |  31   |  Y  | N  | N  | N  | N  | N  | N  |
|     s_opb_i_reg     | Flip-flop |  31   |  Y  | N  | N  | N  | N  | N  | N  |
|     s_expa_reg      | Flip-flop |   8   |  Y  | N  | N  | N  | N  | N  | N  |
|     s_expb_reg      | Flip-flop |   8   |  Y  | N  | N  | N  | N  | N  | N  |
|    s_qutnt_i_reg    | Flip-flop |  27   |  Y  | N  | N  | N  | N  | N  | N  |
|    s_rmndr_i_reg    | Flip-flop |  27   |  Y  | N  | N  | N  | N  | N  | N  |
|   s_exp_10_i_reg    | Flip-flop |  10   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_post_norm_div line 127 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_div.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    output_o_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      ine_o_reg      | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_post_norm_div line 160 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_div.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     s_expo1_reg     | Flip-flop |   9   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_post_norm_div line 166 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_div.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     s_shr1_reg      | Flip-flop |   6   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_post_norm_div line 169 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_div.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     s_shl1_reg      | Flip-flop |   6   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_post_norm_div line 176 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_div.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    s_fraco1_reg     | Flip-flop |  27   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_post_norm_div line 238 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_div.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    s_fraco2_reg     | Flip-flop |  23   |  Y  | N  | N  | N  | N  | N  | N  |
|     s_expo3_reg     | Flip-flop |   9   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_post_norm_addsub line 121 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_addsub.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    output_o_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      ine_o_reg      | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_post_norm_addsub line 171 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_addsub.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    s_expo9_1_reg    | Flip-flop |   9   |  Y  | N  | N  | N  | N  | N  | N  |
|     s_shr1_reg      | Flip-flop |   6   |  Y  | N  | N  | N  | N  | N  | N  |
|     s_shl1_reg      | Flip-flop |   6   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_post_norm_addsub line 202 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_addsub.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|  s_fracto28_1_reg   | Flip-flop |  28   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_mul line 92 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_mul.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|   s_fracta_i_reg    | Flip-flop |  24   |  Y  | N  | N  | N  | N  | N  | N  |
|   s_fractb_i_reg    | Flip-flop |  24   |  Y  | N  | N  | N  | N  | N  | N  |
|    s_start_i_reg    | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_mul line 102 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_mul.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     fract_o_reg     | Flip-flop |  48   |  Y  | N  | N  | N  | N  | N  | N  |
|     sign_o_reg      | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|     ready_o_reg     | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_mul line 112 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_mul.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     s_count_reg     | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|    s_ready_o_reg    | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|     s_state_reg     | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_mul line 160 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_mul.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    s_fract_o_reg    | Flip-flop |  48   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Statistics for case statements in always block at line 201 in file
        '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           202            |    auto/auto     |
===============================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv line 116 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      opa_r_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv line 120 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    rmode_r1_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv line 123 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    rmode_r2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv line 126 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    rmode_r3_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv line 129 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    fpu_op_r1_reg    | Flip-flop |   3   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv line 132 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    fpu_op_r2_reg    | Flip-flop |   3   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv line 135 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    fpu_op_r3_reg    | Flip-flop |   3   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv line 180 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|   opa_sign_r_reg    | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv line 183 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|   sign_fasu_r_reg   | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv line 201 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      exp_r_reg      | Flip-flop |   8   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv line 208 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     opa_r1_reg      | Flip-flop |  31   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv line 211 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    fract_i2f_reg    | Flip-flop |  48   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv line 219 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     opas_r1_reg     | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv line 222 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     opas_r2_reg     | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv line 227 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      sign_reg       | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv line 286 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|       out_reg       | Flip-flop |  31   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv line 293 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|       out_reg       | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv line 303 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|       ine_reg       | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv line 309 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      snan_reg       | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv line 315 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      zero_reg       | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv_except line 85 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv_except.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     expa_ff_reg     | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv_except line 88 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv_except.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     expb_ff_reg     | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv_except line 91 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv_except.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    infa_f_r_reg     | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv_except line 94 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv_except.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    infb_f_r_reg     | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv_except line 97 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv_except.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    qnan_r_a_reg     | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv_except line 100 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv_except.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    snan_r_a_reg     | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv_except line 109 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv_except.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|       ind_reg       | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv_except line 112 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv_except.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|       inf_reg       | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv_except line 115 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv_except.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      qnan_reg       | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv_except line 118 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv_except.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      snan_reg       | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv_except line 121 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv_except.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     opa_nan_reg     | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv_except line 124 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv_except.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     opb_nan_reg     | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv_except line 127 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv_except.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     opa_inf_reg     | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv_except line 130 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv_except.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     opb_inf_reg     | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv_except line 133 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv_except.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     expa_00_reg     | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv_except line 136 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv_except.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     expb_00_reg     | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv_except line 139 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv_except.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    fracta_00_reg    | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv_except line 142 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv_except.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    fractb_00_reg    | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv_except line 145 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv_except.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     opa_00_reg      | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv_except line 148 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv_except.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     opb_00_reg      | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv_except line 151 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv_except.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     opa_dn_reg      | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_intfloat_conv_except line 154 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv_except.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     opb_dn_reg      | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Statistics for case statements in always block at line 120 in file
        '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_fcmp.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           123            |     auto/no      |
===============================================

Inferred memory devices in process
        in routine or1200_fpu_div line 99 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_div.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    s_dvdnd_i_reg    | Flip-flop |  50   |  Y  | N  | N  | N  | N  | N  | N  |
|    s_dvsor_i_reg    | Flip-flop |  27   |  Y  | N  | N  | N  | N  | N  | N  |
|    s_start_i_reg    | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_div line 118 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_div.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     s_count_reg     | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|     s_state_reg     | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|    s_ready_o_reg    | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_div line 144 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_div.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      s_dvd_reg      | Flip-flop |  27   |  Y  | N  | N  | N  | N  | N  | N  |
|    s_rmndr_o_reg    | Flip-flop |  27   |  Y  | N  | N  | N  | N  | N  | N  |
|    s_qutnt_o_reg    | Flip-flop |  27   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Statistics for case statements in always block at line 364 in file
        '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_arith.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           366            |    auto/auto     |
===============================================

Inferred memory devices in process
        in routine or1200_fpu_arith line 315 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_arith.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     s_opa_i_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     s_opb_i_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|   s_fpu_op_i_reg    | Flip-flop |   3   |  Y  | N  | N  | N  | N  | N  | N  |
|    s_rmode_i_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    s_start_i_reg    | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_arith line 325 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_arith.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    output_o_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      ine_o_reg      | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|   overflow_o_reg    | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|   underflow_o_reg   | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|   div_zero_o_reg    | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|      inf_o_reg      | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|     zero_o_reg      | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|     qnan_o_reg      | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|     snan_o_reg      | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_arith line 338 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_arith.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     s_count_reg     | Flip-flop |   6   |  Y  | N  | N  | N  | N  | N  | N  |
|     s_state_reg     | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|     ready_o_reg     | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_arith line 364 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_arith.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    s_output1_reg    | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     s_ine_o_reg     | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu_addsub line 90 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_addsub.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     fract_o_reg     | Flip-flop |  28   |  Y  | N  | N  | N  | N  | N  | N  |
|     sign_o_reg      | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Statistics for case statements in always block at line 259 in file
        '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           262            |    auto/auto     |
===============================================

Inferred memory devices in process
        in routine or1200_fpu line 206 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    fpu_op_r_reg     | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu line 211 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| fpu_op_valid_re_reg | Flip-flop |   1   |  N  | N  | Y  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu line 222 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     fpcsr_r_reg     | Flip-flop |   9   |  Y  | N  | Y  | N  | N  | N  | N  |
|     fpcsr_r_reg     | Flip-flop |   2   |  Y  | N  | Y  | N  | N  | N  | N  |
|     fpcsr_r_reg     | Flip-flop |   1   |  N  | N  | Y  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu line 328 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    b_is_qnan_reg    | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|    a_is_snan_reg    | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|    b_is_snan_reg    | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|    a_is_qnan_reg    | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu line 342 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    a_is_inf_reg     | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|  a_b_sign_xor_reg   | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|    b_is_inf_reg     | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu line 360 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    a_is_zero_reg    | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|    b_is_zero_reg    | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu line 393 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|  fpu_conv_shr_reg   | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu line 412 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu.v'.
=================================================================================
|     Register Name     |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
=================================================================================
| fpu_op_valid_re_r_reg | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
=================================================================================
Presto compilation completed successfully.
Current design is now '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_pre_norm_mul.db:or1200_fpu_pre_norm_mul'
Loaded 15 designs.
Current design is 'or1200_fpu_pre_norm_mul'.
Running PRESTO HDLC
Compiling source file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu.v
Searching for /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/or1200_defines.v
Searching for /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_defines.v
Opening include file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_defines.v
Searching for /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/or1200_fpu_pre_norm_mul.v
Searching for /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_pre_norm_mul.v
Opening include file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_pre_norm_mul.v
Searching for /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/or1200_fpu_pre_norm_div.v
Searching for /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_pre_norm_div.v
Opening include file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_pre_norm_div.v
Searching for /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/or1200_fpu_pre_norm_addsub.v
Searching for /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_pre_norm_addsub.v
Opening include file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_pre_norm_addsub.v
Searching for /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/or1200_fpu_post_norm_mul.v
Searching for /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_mul.v
Opening include file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_mul.v
Searching for /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/or1200_fpu_post_norm_intfloat_conv.v
Searching for /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_intfloat_conv.v
Opening include file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_intfloat_conv.v
Searching for /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/or1200_fpu_post_norm_div.v
Searching for /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_div.v
Opening include file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_div.v
Searching for /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/or1200_fpu_post_norm_addsub.v
Searching for /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_addsub.v
Opening include file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_post_norm_addsub.v
Searching for /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/or1200_fpu_mul.v
Searching for /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_mul.v
Opening include file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_mul.v
Searching for /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/or1200_fpu_intfloat_conv.v
Searching for /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv.v
Opening include file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv.v
Searching for /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/or1200_fpu_intfloat_conv_except.v
Searching for /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv_except.v
Opening include file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_intfloat_conv_except.v
Searching for /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/or1200_fpu_fcmp.v
Searching for /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_fcmp.v
Opening include file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_fcmp.v
Searching for /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/or1200_fpu_div.v
Searching for /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_div.v
Opening include file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_div.v
Searching for /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/or1200_fpu_arith.v
Searching for /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_arith.v
Opening include file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_arith.v
Searching for /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/or1200_fpu_addsub.v
Searching for /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_addsub.v
Opening include file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu_addsub.v
Presto compilation completed successfully.
Running PRESTO HDLC

Statistics for case statements in always block at line 259 in file
        '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           262            |    auto/auto     |
===============================================

Inferred memory devices in process
        in routine or1200_fpu line 206 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    fpu_op_r_reg     | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu line 211 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| fpu_op_valid_re_reg | Flip-flop |   1   |  N  | N  | Y  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu line 222 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     fpcsr_r_reg     | Flip-flop |   9   |  Y  | N  | Y  | N  | N  | N  | N  |
|     fpcsr_r_reg     | Flip-flop |   2   |  Y  | N  | Y  | N  | N  | N  | N  |
|     fpcsr_r_reg     | Flip-flop |   1   |  N  | N  | Y  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu line 328 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    b_is_qnan_reg    | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|    a_is_snan_reg    | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|    b_is_snan_reg    | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|    a_is_qnan_reg    | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu line 342 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    a_is_inf_reg     | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|  a_b_sign_xor_reg   | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|    b_is_inf_reg     | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu line 360 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    a_is_zero_reg    | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|    b_is_zero_reg    | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu line 393 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|  fpu_conv_shr_reg   | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
        in routine or1200_fpu line 412 in file
                '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu.v'.
=================================================================================
|     Register Name     |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
=================================================================================
| fpu_op_valid_re_r_reg | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
=================================================================================
Presto compilation completed successfully.
Warning: Design 'or1200_fpu' was renamed to 'or1200_fpu_1' to avoid
        a conflict with another design that has the same name but
different parameters. (LINK-17)
Elaborated 1 design.
Current design is now 'or1200_fpu_1'.

  Linking design 'or1200_fpu_1'
  Using the following designs and libraries:
  --------------------------------------------------------------------------
  * (16 designs)              /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/dc/work/or1200_fpu_1.db, etc
  saed90nm_typ_ht (library)   /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/saed90nm_typ_ht.db
  saed90nm_typ_htm (library)  /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/saed90nm_typ_htm.db
  saed90nm_typ_htl (library)  /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/saed90nm_typ_htl.db
  saed90nm_min_htl (library)  /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/saed90nm_min_htl.db
  saed90nm_typ_ht_cg (library) /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/clock_gating/saed90nm_typ_ht_cg.db
  saed90nm_typ_htm_cg (library) /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/clock_gating/saed90nm_typ_htm_cg.db
  saed90nm_typ_htl_cg (library) /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/clock_gating/saed90nm_typ_htl_cg.db
  saed90nm_min_htl_cg (library) /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/clock_gating/saed90nm_min_htl_cg.db
  saed90nm_typ_ht_rd (library) /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/retention/saed90nm_typ_ht_rd.db
  saed90nm_typ_htm_rd (library) /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/retention/saed90nm_typ_htm_rd.db
  saed90nm_typ_htl_rd (library) /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/retention/saed90nm_typ_htl_rd.db
  saed90nm_min_htl_rd (library) /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/retention/saed90nm_min_htl_rd.db
  saed90nm_min_htln_lsh (library) /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters/saed90nm_min_htln_lsh.db
  saed90nm_typ_hthh_lsh (library) /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters/saed90nm_typ_hthh_lsh.db
  saed90nm_typ_hthn_lsh (library) /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters/saed90nm_typ_hthn_lsh.db
  saed90nm_typ_htln_lsh (library) /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters/saed90nm_typ_htln_lsh.db
  saed90nm_max_htln_lsh (library) /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters/saed90nm_max_htln_lsh.db
  saed90nm_typ_hthm_lsh (library) /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters/saed90nm_typ_hthm_lsh.db
  saed90nm_typ_htmm_lsh (library) /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters/saed90nm_typ_htmm_lsh.db
  saed90nm_min_htln_iso (library) /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/isoao/saed90nm_min_htln_iso.db
  saed90nm_typ_hthh_iso (library) /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/isoao/saed90nm_typ_hthh_iso.db
  saed90nm_typ_htln_iso (library) /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/isoao/saed90nm_typ_htln_iso.db
  saed90nm_max_htln_iso (library) /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/isoao/saed90nm_max_htln_iso.db
  saed90nm_typ_htmm_iso (library) /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/isoao/saed90nm_typ_htmm_iso.db
  saed90nm_min_htln_lshss (library) /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters_ss/saed90nm_min_htln_lshss.db
  saed90nm_typ_hthh_lshss (library) /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters_ss/saed90nm_typ_hthh_lshss.db
  saed90nm_typ_hthn_lshss (library) /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters_ss/saed90nm_typ_hthn_lshss.db
  saed90nm_typ_htln_lshss (library) /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters_ss/saed90nm_typ_htln_lshss.db
  saed90nm_max_htln_lshss (library) /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters_ss/saed90nm_max_htln_lshss.db
  saed90nm_typ_hthm_lshss (library) /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters_ss/saed90nm_typ_hthm_lshss.db
  saed90nm_typ_htmm_lshss (library) /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters_ss/saed90nm_typ_htmm_lshss.db



Loading UPF file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/dc/ref/models/design3.upf with version 1.0...
## CREATE POWER DOMAINS
create_power_domain TOP
create_power_domain PD_ARITH -elements {fpu_arith} -scope fpu_arith
create_power_domain PD_CONV -elements {fpu_intfloat_conv} -scope fpu_intfloat_conv
create_power_domain PD_COMP -elements {fpu_fcmp} -scope fpu_fcmp
## SUPPLY NETWORK - PD_ARITH
create_supply_net VDD -domain fpu_arith/PD_ARITH
create_supply_net VSS  -domain fpu_arith/PD_ARITH
create_supply_port VDD -domain fpu_arith/PD_ARITH
create_supply_port VSS  -domain fpu_arith/PD_ARITH
connect_supply_net fpu_arith/VDD -ports {fpu_arith/VDD}
connect_supply_net fpu_arith/VSS -ports {fpu_arith/VSS}
set_domain_supply_net fpu_arith/PD_ARITH -primary_power_net fpu_arith/VDD -primary_ground_net fpu_arith/VSS
## SUPPLY NETWORK - PD_CONV
create_supply_net VDDT -domain fpu_intfloat_conv/PD_CONV
create_supply_net VSS  -domain fpu_intfloat_conv/PD_CONV
create_supply_port VDDT -domain fpu_intfloat_conv/PD_CONV
create_supply_port VSS  -domain fpu_intfloat_conv/PD_CONV
connect_supply_net fpu_intfloat_conv/VDDT -ports {fpu_intfloat_conv/VDDT}
connect_supply_net fpu_intfloat_conv/VSS -ports {fpu_intfloat_conv/VSS}
set_domain_supply_net fpu_intfloat_conv/PD_CONV -primary_power_net fpu_intfloat_conv/VDDT -primary_ground_net fpu_intfloat_conv/VSS
## SUPPLY NETWORK - PD_COMP
create_supply_net VDDT -domain fpu_fcmp/PD_COMP
create_supply_net VSS  -domain fpu_fcmp/PD_COMP
create_supply_port VDDT -domain fpu_fcmp/PD_COMP
create_supply_port VSS  -domain fpu_fcmp/PD_COMP
connect_supply_net fpu_fcmp/VDDT -ports {fpu_fcmp/VDDT}
connect_supply_net fpu_fcmp/VSS -ports {fpu_fcmp/VSS}
set_domain_supply_net fpu_fcmp/PD_COMP -primary_power_net fpu_fcmp/VDDT -primary_ground_net fpu_fcmp/VSS
## SUPPLY NETWORK - TOP
create_supply_port VDD
create_supply_port VSS
create_supply_port VDDT
create_supply_net VDD -domain TOP
create_supply_net VSS -domain TOP
create_supply_net VDDT -domain TOP
set_domain_supply_net TOP -primary_power_net VDD -primary_ground_net VSS
connect_supply_net VDDT -ports {VDDT fpu_intfloat_conv/VDDT fpu_fcmp/VDDT}
connect_supply_net VSS -ports {VSS fpu_arith/VSS fpu_intfloat_conv/VSS fpu_fcmp/VSS}
connect_supply_net VDD -ports {VDD fpu_arith/VDD}
## LEVEL-SHIFTER STRATEGY
set_level_shifter ls_arith -domain fpu_arith/PD_ARITH -applies_to inputs -rule both -location automatic -threshold 0.4 
set_level_shifter ls_conv -domain fpu_intfloat_conv/PD_CONV -applies_to inputs -rule both -location automatic -threshold 0.4 
set_level_shifter ls_comp -domain fpu_fcmp/PD_COMP -applies_to inputs -rule both -location automatic -threshold 0.4 
set_level_shifter ls1_arith -domain fpu_arith/PD_ARITH -applies_to outputs -rule both -location automatic -threshold 0.4 
set_level_shifter ls1_conv -domain fpu_intfloat_conv/PD_CONV -applies_to outputs -rule both -location automatic -threshold 0.4 
set_level_shifter ls1_comp -domain fpu_fcmp/PD_COMP -applies_to outputs -rule both -location automatic -threshold 0.4 
## ISOLATION STRATEGY
set_isolation iso_conv -domain fpu_intfloat_conv/PD_CONV -isolation_power_net fpu_intfloat_conv/VDDT -isolation_ground_net fpu_intfloat_conv/VSS -clamp_value 1 -applies_to outputs -diff_supply_only TRUE
set_isolation_control iso_conv -domain fpu_intfloat_conv/PD_CONV -isolation_signal flag_we
set_isolation iso_comp -domain fpu_fcmp/PD_COMP -isolation_power_net fpu_fcmp/VDDT -isolation_ground_net fpu_fcmp/VSS -clamp_value 1 -applies_to outputs -diff_supply_only TRUE
set_isolation_control iso_comp -domain fpu_fcmp/PD_COMP -isolation_signal flag_we
# POWER STATE TABLE
## CREATE PORT STATES
add_port_state VDD     -state {TOP 1.2}
add_port_state VDDT    -state {BLOCK 0.8}  -state {BLOCK_off off}
add_port_state VSS     -state {TOP 0}
## OPERATING VOLTAGES
create_pst risc_core_pst -supplies         {VDD  VDDT VSS}
add_pst_state s0 -pst risc_core_pst -state {TOP BLOCK TOP}
add_pst_state s1 -pst risc_core_pst -state {TOP BLOCK_off TOP}
#set_port_attributes -elements {fpu_arith} -applies_to outputs #-attribute repeater_power_net fpu_arith/VDD #-attribute repeater_ground_net fpu_arith/VSS
#set_port_attributes -elements {fpu_intfloat_conv} -applies_to inputs #-attribute repeater_power_net VDD -attribute repeater_ground_net VSS
#set_port_attributes -elements {fpu_fcmp} -applies_to inputs #-attribute repeater_power_net VDD -attribute repeater_ground_net VSS

End loading UPF file /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/dc/ref/models/design3.upf
Using operating conditions 'TYPICAL' found in library 'saed90nm_typ_ht'.
 
****************************************
check_design summary:
Version:     F-2011.09-SP2
Date:        Tue May  1 01:45:29 2018
****************************************

                   Name                                            Total
--------------------------------------------------------------------------------
Inputs/Outputs                                                    246
    Unconnected ports (LINT-28)                                    80
    Feedthrough (LINT-29)                                          46
    Shorted outputs (LINT-31)                                      59
    Constant outputs (LINT-52)                                     61

Cells                                                             139
    Cells do not drive (LINT-1)                                    35
    Connected to power or ground (LINT-32)                          1
    Leaf pins connected to undriven nets (LINT-58)                 70
    Cells have undriven hier pins (LINT-59)                        31
    Hier pins without driver and load (LINT-60)                     2

Nets                                                                4
    Unloaded nets (LINT-2)                                          4
--------------------------------------------------------------------------------

Warning: In design 'or1200_fpu_arith', cell 'C633' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_intfloat_conv', cell 'C263' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_intfloat_conv', cell 'C267' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_pre_norm_addsub', cell 'B_8' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_pre_norm_addsub', cell 'B_9' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_pre_norm_addsub', cell 'B_10' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_pre_norm_addsub', cell 'B_11' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_addsub', cell 'C140' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_addsub', cell 'C141' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_addsub', cell 'B_6' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_post_norm_addsub', cell 'C1427' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_post_norm_addsub', cell 'B_26' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_post_norm_addsub', cell 'B_27' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_post_norm_addsub', cell 'B_30' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_post_norm_addsub', cell 'C1570' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_post_norm_addsub', cell 'C1571' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_mul', cell 'C2675' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_mul', cell 'C2709' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_post_norm_mul', cell 'B_23' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_post_norm_mul', cell 'C3877' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_post_norm_mul', cell 'B_25' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_post_norm_mul', cell 'B_26' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_post_norm_mul', cell 'B_28' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_post_norm_mul', cell 'B_29' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_post_norm_mul', cell 'C4141' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_div', cell 'C753' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_div', cell 'C792' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_post_norm_div', cell 'B_19' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_post_norm_div', cell 'B_20' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_post_norm_div', cell 'B_21' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_post_norm_div', cell 'B_28' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_post_norm_div', cell 'C1948' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_post_norm_div', cell 'C1949' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_post_norm_intfloat_conv', cell 'B_30' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_post_norm_intfloat_conv', cell 'B_31' does not drive any nets. (LINT-1)
Warning: In design 'or1200_fpu_1', net 'unordered' driven by pin 'fpu_fcmp/unordered' has no loads. (LINT-2)
Warning: In design 'or1200_fpu_1', net 'overflow_conv' driven by pin 'fpu_intfloat_conv/overflow' has no loads. (LINT-2)
Warning: In design 'or1200_fpu_1', net 'fpu_intfloat_conv/opa_00' driven by pin 'fpu_intfloat_conv/u0/opa_00' has no loads. (LINT-2)
Warning: In design 'or1200_fpu_1', net 'fpu_intfloat_conv/ind_d' driven by pin 'fpu_intfloat_conv/u0/ind' has no loads. (LINT-2)
Warning: In design 'or1200_fpu_1', port 'spr_cs' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_write' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_addr[31]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_addr[30]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_addr[29]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_addr[28]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_addr[27]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_addr[26]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_addr[25]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_addr[24]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_addr[23]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_addr[22]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_addr[21]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_addr[20]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_addr[19]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_addr[18]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_addr[17]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_addr[16]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_addr[15]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_addr[14]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_addr[13]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_addr[12]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_addr[11]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_addr[10]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_addr[9]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_addr[8]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_addr[7]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_addr[6]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_addr[5]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_addr[4]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_addr[3]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_addr[2]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_addr[1]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_addr[0]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_dat_i[31]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_dat_i[30]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_dat_i[29]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_dat_i[28]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_dat_i[27]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_dat_i[26]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_dat_i[25]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_dat_i[24]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_dat_i[23]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_dat_i[22]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_dat_i[21]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_dat_i[20]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_dat_i[19]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_dat_i[18]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_dat_i[17]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_dat_i[16]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_dat_i[15]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_dat_i[14]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_dat_i[13]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_dat_i[12]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_dat_i[11]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_dat_i[10]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_dat_i[9]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_dat_i[8]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_dat_i[7]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_dat_i[6]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_dat_i[5]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_dat_i[4]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_dat_i[3]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_dat_i[2]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_dat_i[1]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_1', port 'spr_dat_i[0]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_pre_norm_addsub', port 'opa_i[31]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_pre_norm_addsub', port 'opb_i[31]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_pre_norm_mul', port 'opa_i[31]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_pre_norm_mul', port 'opb_i[31]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_post_norm_mul', port 'opa_i[31]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_post_norm_mul', port 'opb_i[31]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_pre_norm_div', port 'opa_i[31]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_pre_norm_div', port 'opb_i[31]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_post_norm_div', port 'opa_i[31]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_post_norm_div', port 'opb_i[31]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_intfloat_conv_except', port 'opa[31]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_intfloat_conv_except', port 'opb[31]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_post_norm_intfloat_conv', port 'opa_dn' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_post_norm_intfloat_conv', port 'opb_dn' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opa_i[22]' is connected directly to output port 'fracta_24_o[22]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opa_i[21]' is connected directly to output port 'fracta_24_o[21]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opa_i[20]' is connected directly to output port 'fracta_24_o[20]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opa_i[19]' is connected directly to output port 'fracta_24_o[19]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opa_i[18]' is connected directly to output port 'fracta_24_o[18]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opa_i[17]' is connected directly to output port 'fracta_24_o[17]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opa_i[16]' is connected directly to output port 'fracta_24_o[16]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opa_i[15]' is connected directly to output port 'fracta_24_o[15]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opa_i[14]' is connected directly to output port 'fracta_24_o[14]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opa_i[13]' is connected directly to output port 'fracta_24_o[13]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opa_i[12]' is connected directly to output port 'fracta_24_o[12]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opa_i[11]' is connected directly to output port 'fracta_24_o[11]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opa_i[10]' is connected directly to output port 'fracta_24_o[10]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opa_i[9]' is connected directly to output port 'fracta_24_o[9]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opa_i[8]' is connected directly to output port 'fracta_24_o[8]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opa_i[7]' is connected directly to output port 'fracta_24_o[7]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opa_i[6]' is connected directly to output port 'fracta_24_o[6]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opa_i[5]' is connected directly to output port 'fracta_24_o[5]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opa_i[4]' is connected directly to output port 'fracta_24_o[4]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opa_i[3]' is connected directly to output port 'fracta_24_o[3]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opa_i[2]' is connected directly to output port 'fracta_24_o[2]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opa_i[1]' is connected directly to output port 'fracta_24_o[1]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opa_i[0]' is connected directly to output port 'fracta_24_o[0]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opb_i[22]' is connected directly to output port 'fractb_24_o[22]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opb_i[21]' is connected directly to output port 'fractb_24_o[21]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opb_i[20]' is connected directly to output port 'fractb_24_o[20]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opb_i[19]' is connected directly to output port 'fractb_24_o[19]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opb_i[18]' is connected directly to output port 'fractb_24_o[18]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opb_i[17]' is connected directly to output port 'fractb_24_o[17]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opb_i[16]' is connected directly to output port 'fractb_24_o[16]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opb_i[15]' is connected directly to output port 'fractb_24_o[15]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opb_i[14]' is connected directly to output port 'fractb_24_o[14]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opb_i[13]' is connected directly to output port 'fractb_24_o[13]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opb_i[12]' is connected directly to output port 'fractb_24_o[12]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opb_i[11]' is connected directly to output port 'fractb_24_o[11]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opb_i[10]' is connected directly to output port 'fractb_24_o[10]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opb_i[9]' is connected directly to output port 'fractb_24_o[9]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opb_i[8]' is connected directly to output port 'fractb_24_o[8]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opb_i[7]' is connected directly to output port 'fractb_24_o[7]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opb_i[6]' is connected directly to output port 'fractb_24_o[6]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opb_i[5]' is connected directly to output port 'fractb_24_o[5]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opb_i[4]' is connected directly to output port 'fractb_24_o[4]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opb_i[3]' is connected directly to output port 'fractb_24_o[3]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opb_i[2]' is connected directly to output port 'fractb_24_o[2]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opb_i[1]' is connected directly to output port 'fractb_24_o[1]'. (LINT-29)
Warning: In design 'or1200_fpu_pre_norm_mul', input port 'opb_i[0]' is connected directly to output port 'fractb_24_o[0]'. (LINT-29)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[31]' is connected directly to output port 'spr_dat_o[0]'. (LINT-31)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[31]' is connected directly to output port 'spr_dat_o[1]'. (LINT-31)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[31]' is connected directly to output port 'spr_dat_o[2]'. (LINT-31)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[31]' is connected directly to output port 'spr_dat_o[3]'. (LINT-31)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[31]' is connected directly to output port 'spr_dat_o[4]'. (LINT-31)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[31]' is connected directly to output port 'spr_dat_o[5]'. (LINT-31)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[31]' is connected directly to output port 'spr_dat_o[6]'. (LINT-31)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[31]' is connected directly to output port 'spr_dat_o[7]'. (LINT-31)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[31]' is connected directly to output port 'spr_dat_o[8]'. (LINT-31)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[31]' is connected directly to output port 'spr_dat_o[9]'. (LINT-31)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[31]' is connected directly to output port 'spr_dat_o[10]'. (LINT-31)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[31]' is connected directly to output port 'spr_dat_o[11]'. (LINT-31)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[31]' is connected directly to output port 'spr_dat_o[12]'. (LINT-31)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[31]' is connected directly to output port 'spr_dat_o[13]'. (LINT-31)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[31]' is connected directly to output port 'spr_dat_o[14]'. (LINT-31)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[31]' is connected directly to output port 'spr_dat_o[15]'. (LINT-31)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[31]' is connected directly to output port 'spr_dat_o[16]'. (LINT-31)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[31]' is connected directly to output port 'spr_dat_o[17]'. (LINT-31)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[31]' is connected directly to output port 'spr_dat_o[18]'. (LINT-31)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[31]' is connected directly to output port 'spr_dat_o[19]'. (LINT-31)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[31]' is connected directly to output port 'spr_dat_o[20]'. (LINT-31)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[31]' is connected directly to output port 'spr_dat_o[21]'. (LINT-31)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[31]' is connected directly to output port 'spr_dat_o[22]'. (LINT-31)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[31]' is connected directly to output port 'spr_dat_o[23]'. (LINT-31)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[31]' is connected directly to output port 'spr_dat_o[24]'. (LINT-31)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[31]' is connected directly to output port 'spr_dat_o[25]'. (LINT-31)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[31]' is connected directly to output port 'spr_dat_o[26]'. (LINT-31)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[31]' is connected directly to output port 'spr_dat_o[27]'. (LINT-31)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[31]' is connected directly to output port 'spr_dat_o[28]'. (LINT-31)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[31]' is connected directly to output port 'spr_dat_o[29]'. (LINT-31)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[31]' is connected directly to output port 'spr_dat_o[30]'. (LINT-31)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[25]' is connected directly to output port 'dvsor_27_o[24]'. (LINT-31)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[25]' is connected directly to output port 'dvsor_27_o[25]'. (LINT-31)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[25]' is connected directly to output port 'dvsor_27_o[26]'. (LINT-31)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[25]' is connected directly to output port 'dvdnd_50_o[0]'. (LINT-31)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[25]' is connected directly to output port 'dvdnd_50_o[1]'. (LINT-31)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[25]' is connected directly to output port 'dvdnd_50_o[2]'. (LINT-31)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[25]' is connected directly to output port 'dvdnd_50_o[3]'. (LINT-31)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[25]' is connected directly to output port 'dvdnd_50_o[4]'. (LINT-31)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[25]' is connected directly to output port 'dvdnd_50_o[5]'. (LINT-31)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[25]' is connected directly to output port 'dvdnd_50_o[6]'. (LINT-31)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[25]' is connected directly to output port 'dvdnd_50_o[7]'. (LINT-31)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[25]' is connected directly to output port 'dvdnd_50_o[8]'. (LINT-31)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[25]' is connected directly to output port 'dvdnd_50_o[9]'. (LINT-31)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[25]' is connected directly to output port 'dvdnd_50_o[10]'. (LINT-31)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[25]' is connected directly to output port 'dvdnd_50_o[11]'. (LINT-31)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[25]' is connected directly to output port 'dvdnd_50_o[12]'. (LINT-31)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[25]' is connected directly to output port 'dvdnd_50_o[13]'. (LINT-31)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[25]' is connected directly to output port 'dvdnd_50_o[14]'. (LINT-31)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[25]' is connected directly to output port 'dvdnd_50_o[15]'. (LINT-31)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[25]' is connected directly to output port 'dvdnd_50_o[16]'. (LINT-31)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[25]' is connected directly to output port 'dvdnd_50_o[17]'. (LINT-31)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[25]' is connected directly to output port 'dvdnd_50_o[18]'. (LINT-31)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[25]' is connected directly to output port 'dvdnd_50_o[19]'. (LINT-31)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[25]' is connected directly to output port 'dvdnd_50_o[20]'. (LINT-31)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[25]' is connected directly to output port 'dvdnd_50_o[21]'. (LINT-31)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[25]' is connected directly to output port 'dvdnd_50_o[22]'. (LINT-31)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[25]' is connected directly to output port 'dvdnd_50_o[23]'. (LINT-31)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[25]' is connected directly to output port 'dvdnd_50_o[24]'. (LINT-31)
Warning: In design 'or1200_fpu_1', a pin on submodule 'fpu_arith' is connected to logic 1 or logic 0. (LINT-32)
   Pin 'fpu_op_i[2]' is connected to logic 0. 
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[31]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[30]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[29]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[28]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[27]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[26]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[25]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[24]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[23]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[22]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[21]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[20]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[19]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[18]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[17]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[16]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[15]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[14]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[13]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[12]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[11]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[10]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[9]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[8]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[7]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[6]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[5]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[4]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[3]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[2]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[1]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_1', output port 'spr_dat_o[0]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[25]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[24]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[23]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[22]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[21]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[20]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[19]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[18]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[17]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[16]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[15]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[14]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[13]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[12]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[11]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[10]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[9]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[8]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[7]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[6]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[5]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[4]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[3]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[2]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[1]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvdnd_50_o[0]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvsor_27_o[26]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvsor_27_o[25]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_pre_norm_div', output port 'dvsor_27_o[24]' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C33' is connected to undriven net 'opb[23]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C34' is connected to undriven net 'opb[24]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C35' is connected to undriven net 'opb[25]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C36' is connected to undriven net 'opb[26]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C37' is connected to undriven net 'opb[27]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C38' is connected to undriven net 'opb[28]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'A' of leaf cell 'C39' is connected to undriven net 'opb[30]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C39' is connected to undriven net 'opb[29]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C64' is connected to undriven net 'opb[0]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C65' is connected to undriven net 'opb[1]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C66' is connected to undriven net 'opb[2]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C67' is connected to undriven net 'opb[3]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C68' is connected to undriven net 'opb[4]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C69' is connected to undriven net 'opb[5]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C70' is connected to undriven net 'opb[6]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C71' is connected to undriven net 'opb[7]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C72' is connected to undriven net 'opb[8]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C73' is connected to undriven net 'opb[9]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C74' is connected to undriven net 'opb[10]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C75' is connected to undriven net 'opb[11]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C76' is connected to undriven net 'opb[12]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C77' is connected to undriven net 'opb[13]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C78' is connected to undriven net 'opb[14]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C79' is connected to undriven net 'opb[15]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C80' is connected to undriven net 'opb[16]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C81' is connected to undriven net 'opb[17]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C82' is connected to undriven net 'opb[18]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C83' is connected to undriven net 'opb[19]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C84' is connected to undriven net 'opb[20]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'A' of leaf cell 'C85' is connected to undriven net 'opb[22]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C85' is connected to undriven net 'opb[21]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C144' is connected to undriven net 'opb[23]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C145' is connected to undriven net 'opb[24]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C146' is connected to undriven net 'opb[25]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C147' is connected to undriven net 'opb[26]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C148' is connected to undriven net 'opb[27]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C149' is connected to undriven net 'opb[28]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'A' of leaf cell 'C150' is connected to undriven net 'opb[30]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C150' is connected to undriven net 'opb[29]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C151' is connected to undriven net 'opb[0]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C152' is connected to undriven net 'opb[1]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C153' is connected to undriven net 'opb[2]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C154' is connected to undriven net 'opb[3]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C155' is connected to undriven net 'opb[4]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C156' is connected to undriven net 'opb[5]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C157' is connected to undriven net 'opb[6]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C158' is connected to undriven net 'opb[7]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C159' is connected to undriven net 'opb[8]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C160' is connected to undriven net 'opb[9]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C161' is connected to undriven net 'opb[10]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C162' is connected to undriven net 'opb[11]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C163' is connected to undriven net 'opb[12]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C164' is connected to undriven net 'opb[13]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C165' is connected to undriven net 'opb[14]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C166' is connected to undriven net 'opb[15]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C167' is connected to undriven net 'opb[16]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C168' is connected to undriven net 'opb[17]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C169' is connected to undriven net 'opb[18]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C170' is connected to undriven net 'opb[19]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C171' is connected to undriven net 'opb[20]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'A' of leaf cell 'C172' is connected to undriven net 'opb[22]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C172' is connected to undriven net 'opb[21]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C184' is connected to undriven net 'opb[23]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C185' is connected to undriven net 'opb[24]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C186' is connected to undriven net 'opb[25]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C187' is connected to undriven net 'opb[26]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C188' is connected to undriven net 'opb[27]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C189' is connected to undriven net 'opb[28]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'A' of leaf cell 'C190' is connected to undriven net 'opb[30]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv_except', input pin 'B' of leaf cell 'C190' is connected to undriven net 'opb[29]'.  (LINT-58)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb[30]' of hierarchical cell 'u0' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb[29]' of hierarchical cell 'u0' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb[28]' of hierarchical cell 'u0' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb[27]' of hierarchical cell 'u0' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb[26]' of hierarchical cell 'u0' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb[25]' of hierarchical cell 'u0' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb[24]' of hierarchical cell 'u0' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb[23]' of hierarchical cell 'u0' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb[22]' of hierarchical cell 'u0' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb[21]' of hierarchical cell 'u0' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb[20]' of hierarchical cell 'u0' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb[19]' of hierarchical cell 'u0' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb[18]' of hierarchical cell 'u0' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb[17]' of hierarchical cell 'u0' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb[16]' of hierarchical cell 'u0' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb[15]' of hierarchical cell 'u0' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb[14]' of hierarchical cell 'u0' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb[13]' of hierarchical cell 'u0' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb[12]' of hierarchical cell 'u0' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb[11]' of hierarchical cell 'u0' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb[10]' of hierarchical cell 'u0' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb[9]' of hierarchical cell 'u0' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb[8]' of hierarchical cell 'u0' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb[7]' of hierarchical cell 'u0' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb[6]' of hierarchical cell 'u0' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb[5]' of hierarchical cell 'u0' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb[4]' of hierarchical cell 'u0' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb[3]' of hierarchical cell 'u0' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb[2]' of hierarchical cell 'u0' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb[1]' of hierarchical cell 'u0' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb[0]' of hierarchical cell 'u0' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb[31]' of hierarchical cell 'u0' has no internal loads and is not connected to any nets. (LINT-60)
Warning: In design 'or1200_fpu_intfloat_conv', input pin 'opb_dn' of hierarchical cell 'u4' has no internal loads and is not connected to any nets. (LINT-60)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Warning: Design rule attributes from the driving cell will be
        set on the port. (UID-401)
Information: set_input_delay values are added to the propagated clock skew. (TIM-113)
Warning: Clock transition specified for propagated clock `clk` will be ignored.  (UID-480)
Warning: Clock transition specified for propagated clock `clk` will be ignored.  (UID-480)
Alib files are up-to-date.
Loading db file '/app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/dw_foundation.sldb'
Information: Failed to find dw_foundation.sldb in the user defined search_path, load it from 'Synopsys Root'. (UISN-70)
Warning: DesignWare synthetic library dw_foundation.sldb is added to the synthetic_library in the current command. (UISN-40)
Information: Evaluating DesignWare library utilization. (UISN-27)

============================================================================
| DesignWare Building Block Library  |         Version         | Available |
============================================================================
| Basic DW Building Blocks           | F-2011.09-DWBB_201109.2 |     *     |
| Licensed DW Building Blocks        | F-2011.09-DWBB_201109.2 |     *     |
============================================================================


Information: There are 391 potential problems in your design. Please run 'check_design' for more information. (LINT-99)


--------------------------------------------------------------------------------
                         Always On Checks Summary
--------------------------------------------------------------------------------
Warning: Ports found with no related supply net. May cause simulation/synthesis/verification mismatch. (UPF-405)

Loaded alib file './alib-52/saed90nm_typ_htl.db.alib'
Loaded alib file './alib-52/saed90nm_typ_htl_cg.db.alib' (placeholder)
Loaded alib file './alib-52/saed90nm_typ_htl_rd.db.alib' (placeholder)
Loaded alib file './alib-52/saed90nm_typ_htln_lsh.db.alib' (placeholder)
Loaded alib file './alib-52/saed90nm_typ_htln_iso.db.alib' (placeholder)
Loaded alib file './alib-52/saed90nm_typ_htln_lshss.db.alib' (placeholder)
Loaded alib file './alib-52/saed90nm_typ_ht.db.alib'
Loaded alib file './alib-52/saed90nm_typ_ht_cg.db.alib' (placeholder)
Loaded alib file './alib-52/saed90nm_typ_ht_rd.db.alib' (placeholder)
Loaded alib file './alib-52/saed90nm_typ_hthh_lsh.db.alib' (placeholder)
Loaded alib file './alib-52/saed90nm_typ_hthn_lsh.db.alib' (placeholder)
Loaded alib file './alib-52/saed90nm_typ_hthm_lsh.db.alib' (placeholder)
Loaded alib file './alib-52/saed90nm_typ_hthh_iso.db.alib' (placeholder)
Loaded alib file './alib-52/saed90nm_typ_hthh_lshss.db.alib' (placeholder)
Loaded alib file './alib-52/saed90nm_typ_hthn_lshss.db.alib' (placeholder)
Loaded alib file './alib-52/saed90nm_typ_hthm_lshss.db.alib' (placeholder)
Info: Cannot ungroup fpu_arith because supply objects are attached to it
Information: The operating condition of the parent cell or1200_fpu_1 is different from that of the child cell fpu_intfloat_conv in the design or1200_fpu_intfloat_conv. The child cell will not be ungrouped. (MV-004)
Information: The operating condition of the parent cell or1200_fpu_1 is different from that of the child cell fpu_fcmp in the design or1200_fpu_fcmp. The child cell will not be ungrouped. (MV-004)
Information: Ungrouping hierarchy fpu_arith/fpu_prenorm_addsub before Pass 1 (OPT-776)
Information: Ungrouping hierarchy fpu_arith/fpu_addsub before Pass 1 (OPT-776)
Information: Ungrouping hierarchy fpu_arith/fpu_pre_norm_mul before Pass 1 (OPT-776)
Information: Ungrouping hierarchy fpu_arith/fpu_pre_norm_div before Pass 1 (OPT-776)
Information: Ungrouping hierarchy fpu_intfloat_conv/u0 before Pass 1 (OPT-776)
Information: Ungrouping 5 of 15 hierarchies before Pass 1 (OPT-775)

  Beginning Pass 1 Mapping
  ------------------------
  Processing 'or1200_fpu_post_norm_mul'
Information: In design 'or1200_fpu_post_norm_mul', the register 's_opb_i_reg[23]' is removed because it is merged to 's_expb_reg[0]'. (OPT-1215)
Information: In design 'or1200_fpu_post_norm_mul', the register 's_opb_i_reg[24]' is removed because it is merged to 's_expb_reg[1]'. (OPT-1215)
Information: In design 'or1200_fpu_post_norm_mul', the register 's_opb_i_reg[25]' is removed because it is merged to 's_expb_reg[2]'. (OPT-1215)
Information: In design 'or1200_fpu_post_norm_mul', the register 's_opb_i_reg[26]' is removed because it is merged to 's_expb_reg[3]'. (OPT-1215)
Information: In design 'or1200_fpu_post_norm_mul', the register 's_opb_i_reg[27]' is removed because it is merged to 's_expb_reg[4]'. (OPT-1215)
Information: In design 'or1200_fpu_post_norm_mul', the register 's_opb_i_reg[28]' is removed because it is merged to 's_expb_reg[5]'. (OPT-1215)
Information: In design 'or1200_fpu_post_norm_mul', the register 's_opb_i_reg[29]' is removed because it is merged to 's_expb_reg[6]'. (OPT-1215)
Information: In design 'or1200_fpu_post_norm_mul', the register 's_opb_i_reg[30]' is removed because it is merged to 's_expb_reg[7]'. (OPT-1215)
Information: In design 'or1200_fpu_post_norm_mul', the register 's_opa_i_reg[23]' is removed because it is merged to 's_expa_reg[0]'. (OPT-1215)
Information: In design 'or1200_fpu_post_norm_mul', the register 's_opa_i_reg[24]' is removed because it is merged to 's_expa_reg[1]'. (OPT-1215)
Information: In design 'or1200_fpu_post_norm_mul', the register 's_opa_i_reg[25]' is removed because it is merged to 's_expa_reg[2]'. (OPT-1215)
Information: In design 'or1200_fpu_post_norm_mul', the register 's_opa_i_reg[26]' is removed because it is merged to 's_expa_reg[3]'. (OPT-1215)
Information: In design 'or1200_fpu_post_norm_mul', the register 's_opa_i_reg[27]' is removed because it is merged to 's_expa_reg[4]'. (OPT-1215)
Information: In design 'or1200_fpu_post_norm_mul', the register 's_opa_i_reg[28]' is removed because it is merged to 's_expa_reg[5]'. (OPT-1215)
Information: In design 'or1200_fpu_post_norm_mul', the register 's_opa_i_reg[29]' is removed because it is merged to 's_expa_reg[6]'. (OPT-1215)
Information: In design 'or1200_fpu_post_norm_mul', the register 's_opa_i_reg[30]' is removed because it is merged to 's_expa_reg[7]'. (OPT-1215)
 Implement Synthetic for 'or1200_fpu_post_norm_mul'.
Information: The register 's_expo1_reg[8]' is a constant and will be removed. (OPT-1206)
  Processing 'or1200_fpu_arith'
Information: The register 'fpu_pre_norm_div/s_expa_in_reg[9]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_pre_norm_div/s_expb_in_reg[9]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_prenorm_addsub/fracta_28_o_reg[27]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_prenorm_addsub/fractb_28_o_reg[27]' is a constant and will be removed. (OPT-1206)
 Implement Synthetic for 'or1200_fpu_arith'.
  Processing 'or1200_fpu_mul'
 Implement Synthetic for 'or1200_fpu_mul'.
  Processing 'or1200_fpu_post_norm_div'
Information: The register 's_shl1_reg[1]' is a constant and will be removed. (OPT-1206)
Information: The register 's_shl1_reg[2]' is a constant and will be removed. (OPT-1206)
Information: The register 's_shl1_reg[3]' is a constant and will be removed. (OPT-1206)
Information: The register 's_shl1_reg[4]' is a constant and will be removed. (OPT-1206)
Information: The register 's_shl1_reg[5]' is a constant and will be removed. (OPT-1206)
Information: In design 'or1200_fpu_post_norm_div', the register 's_opb_i_reg[23]' is removed because it is merged to 's_expb_reg[0]'. (OPT-1215)
Information: In design 'or1200_fpu_post_norm_div', the register 's_opb_i_reg[24]' is removed because it is merged to 's_expb_reg[1]'. (OPT-1215)
Information: In design 'or1200_fpu_post_norm_div', the register 's_opb_i_reg[25]' is removed because it is merged to 's_expb_reg[2]'. (OPT-1215)
Information: In design 'or1200_fpu_post_norm_div', the register 's_opb_i_reg[26]' is removed because it is merged to 's_expb_reg[3]'. (OPT-1215)
Information: In design 'or1200_fpu_post_norm_div', the register 's_opb_i_reg[27]' is removed because it is merged to 's_expb_reg[4]'. (OPT-1215)
Information: In design 'or1200_fpu_post_norm_div', the register 's_opb_i_reg[28]' is removed because it is merged to 's_expb_reg[5]'. (OPT-1215)
Information: In design 'or1200_fpu_post_norm_div', the register 's_opb_i_reg[29]' is removed because it is merged to 's_expb_reg[6]'. (OPT-1215)
Information: In design 'or1200_fpu_post_norm_div', the register 's_opb_i_reg[30]' is removed because it is merged to 's_expb_reg[7]'. (OPT-1215)
Information: In design 'or1200_fpu_post_norm_div', the register 's_opa_i_reg[23]' is removed because it is merged to 's_expa_reg[0]'. (OPT-1215)
Information: In design 'or1200_fpu_post_norm_div', the register 's_opa_i_reg[24]' is removed because it is merged to 's_expa_reg[1]'. (OPT-1215)
Information: In design 'or1200_fpu_post_norm_div', the register 's_opa_i_reg[25]' is removed because it is merged to 's_expa_reg[2]'. (OPT-1215)
Information: In design 'or1200_fpu_post_norm_div', the register 's_opa_i_reg[26]' is removed because it is merged to 's_expa_reg[3]'. (OPT-1215)
Information: In design 'or1200_fpu_post_norm_div', the register 's_opa_i_reg[27]' is removed because it is merged to 's_expa_reg[4]'. (OPT-1215)
Information: In design 'or1200_fpu_post_norm_div', the register 's_opa_i_reg[28]' is removed because it is merged to 's_expa_reg[5]'. (OPT-1215)
Information: In design 'or1200_fpu_post_norm_div', the register 's_opa_i_reg[29]' is removed because it is merged to 's_expa_reg[6]'. (OPT-1215)
Information: In design 'or1200_fpu_post_norm_div', the register 's_opa_i_reg[30]' is removed because it is merged to 's_expa_reg[7]'. (OPT-1215)
 Implement Synthetic for 'or1200_fpu_post_norm_div'.
Information: Added key list 'DesignWare' to design 'or1200_fpu_post_norm_div'. (DDB-72)
  Processing 'or1200_fpu_post_norm_intfloat_conv'
 Implement Synthetic for 'or1200_fpu_post_norm_intfloat_conv'.
  Processing 'or1200_fpu_fcmp'
Information: Added key list 'DesignWare' to design 'or1200_fpu_fcmp'. (DDB-72)
 Implement Synthetic for 'or1200_fpu_fcmp'.
  Processing 'or1200_fpu_intfloat_conv'
Information: In design 'or1200_fpu_intfloat_conv', the register 'opa_r1_reg[22]' is removed because it is merged to 'u0/qnan_r_a_reg'. (OPT-1215)
Information: In design 'or1200_fpu_intfloat_conv', the register 'opa_sign_r_reg' is removed because it is merged to 'opas_r1_reg'. (OPT-1215)
Information: In design 'or1200_fpu_intfloat_conv', the register 'sign_fasu_r_reg' is removed because it is merged to 'opas_r2_reg'. (OPT-1215)
 Implement Synthetic for 'or1200_fpu_intfloat_conv'.
  Processing 'or1200_fpu_1'
  Processing 'or1200_fpu_div'
 Implement Synthetic for 'or1200_fpu_div'.
  Processing 'or1200_fpu_post_norm_addsub'
Information: The register 's_shr1_reg[1]' is a constant and will be removed. (OPT-1206)
Information: The register 's_shr1_reg[2]' is a constant and will be removed. (OPT-1206)
Information: The register 's_shr1_reg[3]' is a constant and will be removed. (OPT-1206)
Information: The register 's_shr1_reg[4]' is a constant and will be removed. (OPT-1206)
Information: The register 's_shr1_reg[5]' is a constant and will be removed. (OPT-1206)
 Implement Synthetic for 'or1200_fpu_post_norm_addsub'.
Information: Added key list 'DesignWare' to design 'or1200_fpu_post_norm_addsub'. (DDB-72)
Information: The register 's_expo9_1_reg[8]' is a constant and will be removed. (OPT-1206)

  Updating timing information
Information: Updating design information... (UID-85)
Information: Input delay ('fall') on clock port 'clk' will be added to the clock's propagated skew. (TIM-112)
Information: Input delay ('rise') on clock port 'clk' will be added to the clock's propagated skew. (TIM-112)
Warning: Net driven by fpu_intfloat_conv/C312/Q is not eligible for isolation insertion with source/sink as it is not loaded. (UPF-213)
Warning: Net driven by fpu_fcmp/C826/Q is not eligible for isolation insertion with source/sink as it is not loaded. (UPF-213)
Information: Total 42 isolation cells are inserted. (UPF-214)
Information: Total 0 level shifters are removed. (MV-238)
Information: Total 0 level shifters are inserted. (MV-239)
Warning: 158 nets has level shifter constraints but no level shifters are inserted. (MV-614)
Information: The register 'fpu_arith/fpu_div/s_dvsor_i_reg[24]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_arith/fpu_div/s_dvsor_i_reg[25]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_arith/fpu_div/s_dvsor_i_reg[26]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_arith/fpu_div/s_dvdnd_i_reg[0]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_arith/fpu_div/s_dvdnd_i_reg[1]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_arith/fpu_div/s_dvdnd_i_reg[2]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_arith/fpu_div/s_dvdnd_i_reg[3]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_arith/fpu_div/s_dvdnd_i_reg[4]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_arith/fpu_div/s_dvdnd_i_reg[5]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_arith/fpu_div/s_dvdnd_i_reg[6]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_arith/fpu_div/s_dvdnd_i_reg[7]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_arith/fpu_div/s_dvdnd_i_reg[8]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_arith/fpu_div/s_dvdnd_i_reg[9]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_arith/fpu_div/s_dvdnd_i_reg[10]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_arith/fpu_div/s_dvdnd_i_reg[11]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_arith/fpu_div/s_dvdnd_i_reg[12]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_arith/fpu_div/s_dvdnd_i_reg[13]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_arith/fpu_div/s_dvdnd_i_reg[14]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_arith/fpu_div/s_dvdnd_i_reg[15]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_arith/fpu_div/s_dvdnd_i_reg[16]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_arith/fpu_div/s_dvdnd_i_reg[17]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_arith/fpu_div/s_dvdnd_i_reg[18]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_arith/fpu_div/s_dvdnd_i_reg[19]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_arith/fpu_div/s_dvdnd_i_reg[20]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_arith/fpu_div/s_dvdnd_i_reg[21]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_arith/fpu_div/s_dvdnd_i_reg[22]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_arith/fpu_div/s_dvdnd_i_reg[23]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_arith/fpu_div/s_dvdnd_i_reg[24]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_arith/fpu_div/s_dvdnd_i_reg[25]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_arith/s_fpu_op_i_reg[2]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_arith/fpu_div/s_dvd_reg[0]' is a constant and will be removed. (OPT-1206)
Information: In design 'or1200_fpu_1', the register 'fpu_intfloat_conv/u0/inf_reg' is removed because it is merged to 'fpu_intfloat_conv/u0/opa_inf_reg'. (OPT-1215)

  Beginning Mapping Optimizations  (Ultra High effort)
  -------------------------------
Information: Added key list 'DesignWare' to design 'or1200_fpu_post_norm_intfloat_conv'. (DDB-72)
Information: Added key list 'DesignWare' to design 'or1200_fpu_arith'. (DDB-72)
Information: Added key list 'DesignWare' to design 'or1200_fpu_post_norm_mul'. (DDB-72)
Information: Added key list 'DesignWare' to design 'or1200_fpu_mul'. (DDB-72)
Information: Added key list 'DesignWare' to design 'or1200_fpu_div'. (DDB-72)
Information: Input delay ('fall') on clock port 'clk' will be added to the clock's propagated skew. (TIM-112)
Information: Input delay ('rise') on clock port 'clk' will be added to the clock's propagated skew. (TIM-112)
Information: Added key list 'DesignWare' to design 'or1200_fpu_intfloat_conv'. (DDB-72)
Info: Cannot ungroup fpu_arith because supply objects are attached to it
Information: Input delay ('fall') on clock port 'clk' will be added to the clock's propagated skew. (TIM-112)
Information: Input delay ('rise') on clock port 'clk' will be added to the clock's propagated skew. (TIM-112)
Information: The register 'fpu_arith/fpu_pre_norm_div/s_expa_in_reg[8]' is a constant and will be removed. (OPT-1206)
Information: The register 'fpu_arith/fpu_pre_norm_div/s_expb_in_reg[8]' is a constant and will be removed. (OPT-1206)

   ELAPSED            WORST NEG TOTAL NEG  DESIGN                            
    TIME      AREA      SLACK     SLACK   RULE COST         ENDPOINT         
  --------- --------- --------- --------- --------- -------------------------
    0:00:40  104903.6      0.00       0.0       0.0                          
    0:00:40  104903.6      0.00       0.0       0.0                          
    0:00:40  104903.6      0.00       0.0       0.0                          
    0:00:40  104903.6      0.00       0.0       0.0                          
  Re-synthesis Optimization (Phase 1)
  Re-synthesis Optimization (Phase 2)
  Global Optimization (Phase 1)
  Global Optimization (Phase 2)
  Global Optimization (Phase 3)
  Global Optimization (Phase 4)
  Global Optimization (Phase 5)
  Global Optimization (Phase 6)
  Global Optimization (Phase 7)
  Global Optimization (Phase 8)
  Global Optimization (Phase 9)
  Global Optimization (Phase 10)
  Global Optimization (Phase 11)
  Global Optimization (Phase 12)
  Global Optimization (Phase 13)
  Global Optimization (Phase 14)
  Global Optimization (Phase 15)
  Global Optimization (Phase 16)
  Global Optimization (Phase 17)
  Global Optimization (Phase 18)
  Global Optimization (Phase 19)
  Global Optimization (Phase 20)
  Global Optimization (Phase 21)
  Global Optimization (Phase 22)
  Global Optimization (Phase 23)
  Global Optimization (Phase 24)
  Global Optimization (Phase 25)
  Global Optimization (Phase 26)
  Global Optimization (Phase 27)
  Global Optimization (Phase 28)
  Global Optimization (Phase 29)
  Global Optimization (Phase 30)
  Global Optimization (Phase 31)
Information: Input delay ('fall') on clock port 'clk' will be added to the clock's propagated skew. (TIM-112)
Information: Input delay ('rise') on clock port 'clk' will be added to the clock's propagated skew. (TIM-112)
Information: Input delay ('fall') on clock port 'clk' will be added to the clock's propagated skew. (TIM-112)
Information: Input delay ('rise') on clock port 'clk' will be added to the clock's propagated skew. (TIM-112)



  Beginning Delay Optimization Phase
  ----------------------------------

   ELAPSED            WORST NEG TOTAL NEG  DESIGN                            
    TIME      AREA      SLACK     SLACK   RULE COST         ENDPOINT         
  --------- --------- --------- --------- --------- -------------------------
    0:00:44   99781.5      0.00       0.0      63.3                          
    0:00:44   99781.5      0.00       0.0      63.3                          
    0:00:44   99781.5      0.00       0.0      63.3                          
    0:00:44   99781.5      0.00       0.0      63.3                          
    0:00:44   99781.5      0.00       0.0      63.3                          
    0:00:44   99781.5      0.00       0.0      63.3                          
    0:00:44   99781.5      0.00       0.0      63.3                          
    0:00:44   99781.5      0.00       0.0      63.3                          
    0:00:44   99781.5      0.00       0.0      63.3                          
    0:00:44   99781.5      0.00       0.0      63.3                          
    0:00:44   99781.5      0.00       0.0      63.3                          
    0:00:44   99781.5      0.00       0.0      63.3                          
    0:00:44   99781.5      0.00       0.0      63.3                          

  Beginning Delay Optimization
  ----------------------------
    0:00:44   99781.5      0.00       0.0      63.3                          
    0:00:44   99781.5      0.00       0.0      63.3                          
    0:00:44   99781.5      0.00       0.0      63.3                          
    0:00:44   99781.5      0.00       0.0      63.3                          
    0:00:44   99781.5      0.00       0.0      63.3                          
    0:00:45   99781.5      0.00       0.0      63.3                          
    0:00:45   99781.5      0.00       0.0      63.3                          
    0:00:45   99781.5      0.00       0.0      63.3                          
    0:00:45   99781.5      0.00       0.0      63.3                          
    0:00:45   99781.5      0.00       0.0      63.3                          
    0:00:45   99781.5      0.00       0.0      63.3                          
    0:00:45   99781.5      0.00       0.0      63.3                          


  Beginning Design Rule Fixing  (max_transition)  (max_capacitance)
  ----------------------------

   ELAPSED            WORST NEG TOTAL NEG  DESIGN                            
    TIME      AREA      SLACK     SLACK   RULE COST         ENDPOINT         
  --------- --------- --------- --------- --------- -------------------------
    0:00:45   99781.5      0.00       0.0      63.3                          
  Global Optimization (Phase 1)
  Global Optimization (Phase 2)
  Global Optimization (Phase 3)
    0:00:46   99757.7      0.00       0.0       0.0                          
    0:00:47  113334.7      0.00       0.0       0.1                          
    0:00:47  113334.7      0.00       0.0       0.1                          
    0:00:50  113334.7      0.00       0.0       0.1                          
    0:00:50  113334.7      0.00       0.0       0.1                          

   ELAPSED            WORST NEG TOTAL NEG  DESIGN                            
    TIME      AREA      SLACK     SLACK   RULE COST         ENDPOINT         
  --------- --------- --------- --------- --------- -------------------------
    0:00:50  113334.7      0.00       0.0       0.1                          
    0:00:50  113334.7      0.00       0.0       0.1                          
Information: Total 0 level shifters are removed incrementally. (MV-238)
Information: Total 0 level shifters are inserted incrementally. (MV-239)


  Beginning Area-Recovery Phase  (max_area 0)
  -----------------------------

   ELAPSED            WORST NEG TOTAL NEG  DESIGN                            
    TIME      AREA      SLACK     SLACK   RULE COST         ENDPOINT         
  --------- --------- --------- --------- --------- -------------------------
    0:00:51  113334.7      0.00       0.0       0.1                          
  Global Optimization (Phase 1)
  Global Optimization (Phase 2)
  Global Optimization (Phase 3)
  Global Optimization (Phase 4)
  Global Optimization (Phase 5)
  Global Optimization (Phase 6)
  Global Optimization (Phase 1)
  Global Optimization (Phase 2)
  Global Optimization (Phase 3)
  Global Optimization (Phase 4)
  Global Optimization (Phase 5)
  Global Optimization (Phase 6)
  Global Optimization (Phase 7)
  Global Optimization (Phase 8)
  Global Optimization (Phase 9)
  Global Optimization (Phase 10)
  Global Optimization (Phase 11)
  Global Optimization (Phase 12)
  Global Optimization (Phase 13)
  Global Optimization (Phase 14)
  Global Optimization (Phase 15)
  Global Optimization (Phase 16)
  Global Optimization (Phase 17)
  Global Optimization (Phase 18)
  Global Optimization (Phase 19)
  Global Optimization (Phase 20)
  Global Optimization (Phase 21)
  Global Optimization (Phase 22)
  Global Optimization (Phase 23)
  Global Optimization (Phase 24)
  Global Optimization (Phase 25)
  Global Optimization (Phase 26)
  Global Optimization (Phase 27)
  Global Optimization (Phase 28)
  Global Optimization (Phase 29)
  Global Optimization (Phase 30)
    0:01:01   99724.9      0.00       0.0       0.0                          
    0:01:01   99724.9      0.00       0.0       0.0                          
    0:01:01   99724.9      0.00       0.0       0.0                          
    0:01:01   99724.9      0.00       0.0       0.0                          
    0:01:01   99724.9      0.00       0.0       0.0                          
    0:01:01   99724.9      0.00       0.0       0.0                          
    0:01:01   99724.9      0.00       0.0       0.0                          
    0:01:01   99724.9      0.00       0.0       0.0                          
    0:01:01   99724.9      0.00       0.0       0.0                          
    0:01:01   99724.9      0.00       0.0       0.0                          
    0:01:01   99724.9      0.00       0.0       0.0                          
    0:01:01   99724.9      0.00       0.0       0.0                          
    0:01:01   99724.9      0.00       0.0       0.0                          
    0:01:01   99724.9      0.00       0.0       0.0                          
    0:01:01   99724.9      0.00       0.0       0.0                          
    0:01:01   99724.9      0.00       0.0       0.0                          
    0:01:01   99724.9      0.00       0.0       0.0                          
    0:01:01   99724.9      0.00       0.0       0.0                          
    0:01:01   99724.9      0.00       0.0       0.0                          
    0:01:01   99724.9      0.00       0.0       0.0                          
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/saed90nm_typ_ht.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/saed90nm_typ_htm.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/saed90nm_typ_htl.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/saed90nm_min_htl.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/clock_gating/saed90nm_typ_ht_cg.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/clock_gating/saed90nm_typ_htm_cg.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/clock_gating/saed90nm_typ_htl_cg.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/clock_gating/saed90nm_min_htl_cg.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/retention/saed90nm_typ_ht_rd.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/retention/saed90nm_typ_htm_rd.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/retention/saed90nm_typ_htl_rd.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/retention/saed90nm_min_htl_rd.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters/saed90nm_min_htln_lsh.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters/saed90nm_typ_hthh_lsh.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters/saed90nm_typ_hthn_lsh.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters/saed90nm_typ_htln_lsh.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters/saed90nm_max_htln_lsh.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters/saed90nm_typ_hthm_lsh.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters/saed90nm_typ_htmm_lsh.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/isoao/saed90nm_min_htln_iso.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/isoao/saed90nm_typ_hthh_iso.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/isoao/saed90nm_typ_htln_iso.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/isoao/saed90nm_max_htln_iso.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/isoao/saed90nm_typ_htmm_iso.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters_ss/saed90nm_min_htln_lshss.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters_ss/saed90nm_typ_hthh_lshss.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters_ss/saed90nm_typ_hthn_lshss.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters_ss/saed90nm_typ_htln_lshss.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters_ss/saed90nm_max_htln_lshss.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters_ss/saed90nm_typ_hthm_lshss.db'
Loading db file '/app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/level_shifters_ss/saed90nm_typ_htmm_lshss.db'

  Optimization Complete
  ---------------------

--------------------------------------------------------------------------------
                         Always On Checks Summary
--------------------------------------------------------------------------------
Warning: Found 48 isolation cell(s) whose power on state is less always on or unrelated to the power on state of domain connected to its output pin.  (MV-517)
 
****************************************
Report : area
Design : or1200_fpu_1
Version: F-2011.09-SP2
Date   : Tue May  1 01:46:45 2018
****************************************

Information: Updating design information... (UID-85)
Information: Input delay ('fall') on clock port 'clk' will be added to the clock's propagated skew. (TIM-112)
Information: Input delay ('rise') on clock port 'clk' will be added to the clock's propagated skew. (TIM-112)
Library(s) Used:

    saed90nm_typ_ht (File: /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/saed90nm_typ_ht.db)
    saed90nm_typ_htl (File: /app/synopsys/pdk/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/saed90nm_typ_htl.db)

Number of ports:                          223
Number of nets:                           449
Number of cells:                          282
Number of combinational cells:            242
Number of sequential cells:                37
Number of macros:                           0
Number of buf/inv:                         12
Number of references:                      28

Combinational area:       54996.480303
Noncombinational area:    36657.561258
Net Interconnect area:    8070.814786  

Total cell area:          91654.041562
Total area:               99724.856347
 
****************************************
Report : constraint
Design : or1200_fpu_1
Version: F-2011.09-SP2
Date   : Tue May  1 01:46:48 2018
****************************************


                                                   Weighted
    Group (max_delay/setup)      Cost     Weight     Cost
    -----------------------------------------------------
    clk                          0.00      1.00      0.00
    default                      0.00      1.00      0.00
    -----------------------------------------------------
    max_delay/setup                                  0.00

                              Total Neg  Critical
    Group (critical_range)      Slack    Endpoints   Cost
    -----------------------------------------------------
    clk                          0.00         0      0.00
    default                      0.00         0      0.00
    -----------------------------------------------------
    critical_range                                   0.00

                                                   Weighted
    Group (min_delay/hold)       Cost     Weight     Cost
    -----------------------------------------------------
    clk (no fix_hold)            0.00      1.00      0.00
    default                      0.00      1.00      0.00
    -----------------------------------------------------
    min_delay/hold                                   0.00


    Constraint                                       Cost
    -----------------------------------------------------
    min_capacitance                                  0.00 (MET)
    max_transition                                   0.00 (MET)
    max_capacitance                                  0.00 (MET)
    max_delay/setup                                  0.00 (MET)
    critical_range                                   0.00 (MET)


 
****************************************
Report : timing
        -path full
        -delay max
        -max_paths 1
Design : or1200_fpu_1
Version: F-2011.09-SP2
Date   : Tue May  1 01:46:50 2018
****************************************
Wire Load Model Mode: enclosed

  Startpoint: fpu_op_r_reg[2]
              (rising edge-triggered flip-flop clocked by clk)
  Endpoint: result[0] (output port clocked by clk)
  Path Group: clk
  Path Type: max

  Des/Clust/Port     Wire Load Model       Library
  ------------------------------------------------
  or1200_fpu_1       140000                saed90nm_typ_ht

  Point                                    Incr       Path      Voltage
  ---------------------------------------------------------------------
  clock clk (rise edge)                    0.00       0.00      
  clock network delay (propagated)         8.45       8.45      
  fpu_op_r_reg[2]/CLK (DFFX1)              0.00       8.45 r    1.20
  fpu_op_r_reg[2]/QN (DFFX1)               0.30       8.75 r    1.20
  U295/Q (OR2X1)                           1.24       9.99 r    1.20
  U291/ZN (INVX0)                          3.08      13.07 f    1.20
  U227/Q (AND2X1)                          2.80      15.87 f    1.20
  U225/Q (OR2X1)                           0.60      16.47 f    1.20
  result[0] (out)                          0.00      16.47 f    1.20
  data arrival time                                  16.47      

  clock clk (rise edge)                  200.00     200.00      
  clock network delay (propagated)         0.00     200.00      
  clock uncertainty                       -2.00     198.00      
  output external delay                  -70.00     128.00      
  data required time                                128.00      
  ---------------------------------------------------------------------
  data required time                                128.00      
  data arrival time                                 -16.47      
  ---------------------------------------------------------------------
  slack (MET)                                       111.53      


Writing verilog file '/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/dc/results/or1200_fpu_dc.v'.
Warning: Verilog 'assign' or 'tran' statements are written out. (VO-4)
1
dc_shell> start_gui
Current design is 'or1200_fpu_1'.
Current design is 'or1200_fpu_1'.
dc_shell> 